R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1103

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
26.3.2
The status bits (bits 0 to 4) in the slave status register are cleared by writing 0 to the respective
status bit positions. The individual bits are held 1 until 0 is written to (other than the GCAR and
STM bits).
Bit
7
6
5
Slave Status Register (ICSSR)
Bit Name
GCAR
STM
Initial value:
R/W:
0
0
0
Initial Value
Bit:
R
7
0
GCAR
R
6
0
R/W
R
R
R
STM
R
5
0
R/W* R/W* R/W* R/W* R/W*
SSR
4
0
The write value should always be 0.
General Call Address Received
Indicates that the address received from the
bus is a general call address (00H). This status
bit does not cause an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in this register) is set to 1.
Slave Transmit Mode
Indicates whether the current slave transmit
mode is read or write. When this bit is set to 1,
the mode is read. When this bit is set to 0, the
mode is write. This status bit does not cause
an interrupt.
This bit is automatically cleared by hardware
when the SIE bit (bit 2 in the slave control
register) is set to 0 or when the SSR bit (bit 4
in the slave status register) is set to 1.
Description
Reserved
SDE
3
0
Rev. 2.00 May 22, 2009 Page 1033 of 1982
SDT
2
0
SDR
1
0
Section 26 I
SAR
0
0
2
C Bus Interface (IIC)
REJ09B0256-0200

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