R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 219

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.2.3
TTB is used to store the base address of the currently used page table, and so on. The contents of
TTB are not changed unless a software directive is issued. This register can be used freely by
software.
6.2.4
After an MMU exception or address error exception occurs, the virtual address at which the
exception occurred is stored. The contents of this register can be changed by software.
6.2.5
The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should
be performed by a program in the P1 or P2 area.
After MMUCR has been updated, execute one of the following three methods before an access
(including an instruction fetch) to the P0, P3, U0, or store queue area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0,
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating MMUCR, the specific instruction
Initial value:
Initial value:
Initial value:
Initial value:
P3, or U0 area.
does not need to be executed. However, note that the CPU processing performance will be
lowered because the instruction fetch is performed again for the next instruction after
MMUCR has been updated.
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Translation Table Base Register (TTB)
TLB Exception Address Register (TEA)
MMU Control Register (MMUCR)
R/W
R/W
R/W
R/W
31
15
31
15
R/W
R/W
R/W
TEA
R/W
TEA
30
14
30
14
R/W
R/W
R/W
R/W
29
13
29
13
Virtual address at which MMU exception or address error occurred
Virtual address at which MMU exception or address error occurred
R/W
R/W
R/W
R/W
28
12
28
12
R/W
R/W
R/W
R/W
27
11
27
11
R/W
R/W
R/W
R/W
26
10
26
10
R/W
R/W
R/W
R/W
25
25
9
9
R/W
R/W
R/W
R/W
24
24
8
8
TTB
TTB
R/W
R/W
R/W
R/W
23
23
7
7
Section 6 Memory Management Unit (MMU)
Rev. 2.00 May 22, 2009 Page 149 of 1982
R/W
R/W
R/W
R/W
22
22
6
6
R/W
R/W
R/W
R/W
21
21
5
5
R/W
R/W
R/W
R/W
20
20
4
4
R/W
R/W
R/W
R/W
19
19
3
3
REJ09B0256-0200
R/W
R/W
R/W
R/W
18
18
2
2
R/W
R/W
R/W
R/W
17
17
1
1
R/W
R/W
R/W
R/W
16
16
0
0