R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 670

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.4.3
DMA transfer type is dual address mode transfer. A data transfer timing depends on the bus mode,
which has cycle steal mode and burst mode.
(1)
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
14.4, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a write cycle.
Rev. 2.00 May 22, 2009 Page 600 of 1982
REJ09B0256-0200
Dual Address Modes
DMA Transfer Types
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Data buffer
Data buffer
Figure 14.4 Data Flow of Dual Address Mode
DMAC
DMAC
DAR
DAR
SAR
SAR
Second bus cycle
First bus cycle
Transfer destination
Transfer destination
Transfer source
Transfer source
Memory
Memory
module
module
module
module