R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 386

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 10 SuperHyway Bus Bridge (SBR)
10.2.2
PRPRICR controls the SuperHyway bus access priority given to the CPU and the other function
modules.
Rev. 2.00 May 22, 2009 Page 316 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 1 
0
R/W:
R/W:
Bit:
Bit:
Bit Name
SBAPR
SuperHyway Bus Priority Control Resister (PRPRICR)
31
15
R
0
R
0
30
14
R
R
0
0
Initial
Value
All 0
1
29
13
R
R
0
0
28
12
R
R
0
0
R/W
R
R/W
27
11
R
R
0
0
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
SuperHyway Bus Access Priority
Sets whether to give the CPU priority over the other
function modules when accessing the SuperHyway bus.
0: The CPU is given the same priority as the other
1: The CPU is given priority over the other function
Note: With this bit set to 1, when both of the data area
function modules.
modules.
25
R
R
0
9
0
accessed by the CPU and the data area accessed
by the other function modules are placed in the
areas for slow accesses, the CPU may be given
priority, thus disabling accesses by the other
function modules. To avoid this, place the data area
accessed by the CPU or the other function modules
in the DDR-SDRAM area, or set this bit to 0.
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
18
R
R
0
2
0
17
R
R
0
1
0
SBAPR
R/W
16
R
0
0
1

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