R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 563

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(4)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit
0
Initial value:
Initial value:
Bit
31 to 20 LAR
19 to 0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Local Address Register 0 (PCILAR0)
Bit:
Bit:
Bit Name
Bit Name
MBARE
R/W
31
15
R
R
R
0
0
R/W
30
14
R
R
R
0
0
Initial
Value R/W
H'000 SH: R/W
All 0
R/W
Initial
Value
0
29
13
R
R
R
0
0
R/W
PCI: R
SH: R
PCI: R
28
12
R
R
R
0
0
R/W
SH: R/W
PCI: R
R/W
27
11
R
R
R
0
0
Description
Local Address (12 bits)
Specify bits 31 to 20 of the start address in local address
space 0.
The effective bits of LAR depend on the capacity of local
address space 0 as specified in PCILSR0.
The effective bits are as follows:
PCILSR0.LS0([28:20]) = 0 0000 0000: Effective bits are [31:20]
PCILSR0.LS0([28:20]) = 0 0000 0001: Effective bits are [31:21]
PCILSR0.LS0([28:20]) = 0 0000 0011: Effective bits are [31:22]
PCILSR0.LS0([28:20]) = 0 1111 1111: Effective bits are [31:28]
PCILSR0.LS0([28:20]) = 1 1111 1111: Effective bits are [31:29]
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
26
10
R
R
R
0
0
LAR
Description
PCI Memory Base Address Register 1 Enable
The local address space 1 can be accessed by setting
this bit to 1.
0: PCIMBAR1 disabled
1: PCIMBAR1 enabled
|
R/W
25
R
R
R
0
9
0
R/W
|
24
R
R
R
0
8
0
R/W
23
R
R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 493 of 1982
R/W
22
R
R
R
0
6
0
R/W
21
R
R
R
0
5
0
Section 13 PCI Controller (PCIC)
R/W
20
R
R
R
0
4
0
19
R
R
R
R
0
3
0
REJ09B0256-0200
18
R
R
R
R
0
2
0
17
R
R
R
R
0
1
0
16
R
R
R
R
0
0
0

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