R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 740

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Power-Down Mode
Table 18.1 lists the states of the CPU and on-chip peripheral modules in each mode.
Table 18.1 States in Power-Down Modes
Notes: 1. Because power supplies (1.2 V and 3.3 V) other than the 2.5-V power supply are
Rev. 2.00 May 22, 2009 Page 670 of 1982
REJ09B0256-0200
Power-
Down
Mode
Sleep
Software
standby
Module
standby
RTC
power
supply
backup
*
DDR-
SDRAM
power
supply
backup
*
Power-on
reset
Manual
reset
Normal
operation
2
1
*
*
3
3
2. Because power supplies (1.2 V, 2.5 V, and 3.3 V) other than the RTC power supply are
3. To enter both RTC and DDR-SDRAM power supply backup modes, satisfy the
Transition
Condition
SLEEP
instruction
executed with
STBY = 0 in
STBCR
SLEEP
instruction
executed with
STBY = 1 in
STBCR
Corresponding
bit in
MSTPCR0/
MSTPCR1 set
to 1
XRTCSTBI pin
driven low
See section
18.7,
DDR-SDRAM
Power Supply
Backup.
PRESET pin
driven low
MRESET pin
driven low or
software reset
stopped in DDR-SDRAM power supply backup mode, all modules, except for pads of
the DDRIF module, are halted and their register information is not retained.
stopped in RTC power supply backup mode, all modules other than the RTC module
are halted and their register information is not retained.
transition conditions for both of them.
CPG CPU
Run
Halt*
Run
Halt
Halt
Initial
state
Held
Run
8
Halt
(register
contents
retained)
Halt
(register
contents
retained)
Run
Halt
Halt
Initial
state
state
Run
Initial
On-Chip
Memory
Retained Run
Halt
(contents
retained)
Halt
Initial
state
Initial
state
Run
Run
Halt
RTC
Run
Run
Run
Halt
Counter
retained
Counter
retained
Run
On-Chip Peripheral
State
Module
Others
Run
Halt
Selected
modules
halt
Halt
Halt
Initial state Initial state Initial state 
WDT,
GPIO, and
debugging
interface
are held
Run
Pin
Held
Hi-Z
Held
Hi-Z*
Undefined*
Held
Run
4
5
DDR-
SDRAM
AR or SR*
Undefined
(refresh not
performed)
AR or SR*
Undefined
(refresh not
performed)
SR*
Initial state 
Run
6
6
6
Cancellation
- Interrupt
- Power-on
- Manual reset
- NMI or IRQ
- Power-on
- Manual reset
Clear
corresponding
bit in
MSTPCR0/
MSTPCR1 to
0
Power-on
reset
Power-on
reset

reset
reset
S1
*
1
0
0
0
0
1
1
0
7
S0
*
0
1
0
1
0
1
1
0
7