R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1381
![IC SUPERH MPU ROMLESS 499BGA](/photos/12/43/124352/r5s77631y266bgv_sml.jpg)
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
4
3
2
1
0
Bit Name
CWRE
DTBUSY
DTBUSY_TU Undefined
—
REQ
Initial
Value
0
0
0
0
R/W
R
R
R
R
R
Description
Command Register Write Enable
Indicates whether the CMDR command is being
transmitted or has been transmitted.
0: The CMDR command has been transmitted, or the
1: The CMDR command is waiting to be transmitted or
Data Busy
Indicates command execution status. Indicates that the
card is in the busy state after the command sequence
of a command without data transfer which includes the
busy state in the response has ended or a command
with write data has ended.
0: Idle state waiting for a command, or command
1: Card is in the data busy state after command
Data Busy Pin Status
Monitors the levels of the DAT pin in MMC mode. By
reading this bit, whether the card is in the busy state
can be monitored after the card in the busy state has
been deselected and then selected again afterwards.
0: Card indicates data busy.
1: Card indicates not data busy.
Reserved
This bit is always read as 0. The write value should
always be 0.
Interrupt Request
Indicates whether an interrupt is requested. An interrupt
request is the logical OR of the INTSTR0, INTSTR1,
and INTSTR2 flags. Settings of the INTSTR0,
INTSTR1, and INTSTR2 flags are controlled by the
enable bits in INTCR0, INTSTR1, and INTCR2.
0: No interrupt requested.
1: Interrupt requested.
START bit in CMDSTRT has not been set yet, so the
new command can be written.
is being transmitted. If a new command is written, a
malfunction will result.
sequence execution in progress
sequence termination.
Section 31 Multimedia Card Interface (MMCIF)
Rev. 2.00 May 22, 2009 Page 1311 of 1982
REJ09B0256-0200
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