R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 570

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 13 PCI Controller (PCIC)
(7)
This register is the mask register for PCIIR.
Rev. 2.00 May 22, 2009 Page 500 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 15 
14
13 to 10 
9
8
7
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Interrupt Mask Register (PCIIMR)
Bit:
Bit:
Bit Name
TTADIM
TMTOIM
MDEIM
APEDIM
31
15
R
R
R
R
0
0
R/W
TTA
DIM
30
14
R
R
R
0
0
Initial
Value
All 0
0
All 0
0
0
0
29
13
R
R
R
R
0
0
28
12
R
R
R
R
0
0
R/W
SH: R
PCI: R
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
27
11
R
R
R
R
0
0
26
10
R
R
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Target-Abort Interrupt Mask
0: PCIIR.TTADI disabled (masked)
1: PCIIR.TTADI enabled (not masked)
Reserved
These bits are always read as 0. The write value
should always be 0.
Target Retry Time Out Interrupt Mask
0: PCIIR.TMTOI disabled (masked)
1: PCIIR. TMTOI enabled (not masked)
Master Function Disable Error Interrupt Mask
0: PCIIR.MDEI disabled (masked)
1: PCIIR.MDEI enabled (not masked)
Address Parity Error Detection Interrupt Mask
0: PCIIR.APEDI disabled (masked)
1: PCIIR.APEDI enabled (not masked)
R/W
TMT
OIM
25
R
R
R
0
9
0
MDE
R/W
24
IM
R
R
R
0
8
0
APE
R/W
DIM
23
R
R
R
0
7
0
R/W
DIM
SE
22
R
R
R
0
6
0
TWM
DPEI
R/W
21
R
R
R
0
5
0
DPEI
TRM
R/W
20
R
R
R
0
4
0
IMM
R/W
TAD
19
R
R
R
0
3
0
MAD
IMM
R/W
18
R
R
R
0
2
0
PDIM
R/W
MW
17
R
R
R
0
1
0
PEIM
MRD
R/W
16
R
R
R
0
0
0

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