R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 558

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
13.3.3
(1)
PCICR is a 32-bit register which specifies the operation of the PCIC.
The register is write protected; only writes in which the upper eight bits (that is, bits 31 to 24)
have the value H'A5 are performed. All other writes are ignored.
Rev. 2.00 May 22, 2009 Page 488 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Bit
31 to 24 
23 to 12 
11
10
9
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Control Register (PCICR)
Bit:
Bit:
Local Register
Bit Name
PFCS
FTO
PFE
31
15
—
—
R
R
R
R
0
0
30
14
—
—
R
R
R
R
0
0
Initial
Value
H'00
All 0
0
0
0
29
13
—
—
R
R
R
R
0
0
28
12
—
—
R
R
R
R
0
0
R/W
SH: R/W
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
SH: R/W
PCI: R
PFCS
R/W
27
—
11
R
R
R
0
0
FTO
R/W
26
10
—
R
R
R
0
0
PFE
R/W
Description
Reserved
Set these bits to H'A5 only when writing to bits 11 to
8, 6, and 3 to 0.
These bits are always read as 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Pre-Fetch Command Setting
This bit is valid only when the PFE bit is 1.
0: Always 8-byte pre-fetching
1: Always 32-byte pre-fetching
PCI TRDY Control Enable
In a target access, negate the TRDY, within 5 cycles
before disconnection.
0: Disabled
1: Enabled
PCI Pre-Fetch Enable
0: Disabled
1: Enabled
25
—
R
R
R
0
9
0
TBS
R/W
24
—
R
R
R
0
8
0
23
—
—
R
R
R
R
0
7
0
BMAM
R/W
22
—
R
R
R
0
6
0
21
—
—
—
R
R
R
R
0
5
20
—
—
—
R
R
R
R
0
4
19
—
—
R
R
R
R
0
3
0
IOCS
R/W
18
—
R
R
R
0
2
0
R/W
RST
CTL
17
—
R
R
R
0
1
0
R/W
CFI
NIT
16
—
R
R
R
0
0
0