R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 215

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Memory Management Unit (MMU)
Address Translation: When the MMU is used, the virtual address space is divided into units
called pages, and translation to physical addresses is carried out in these page units. The address
translation table in external memory contains the physical addresses corresponding to virtual
addresses and additional information such as memory protection codes. Fast address translation is
achieved by caching the contents of the address translation table located in external memory into
the TLB. In this LSI, basically, the ITLB is used for instruction accesses and the UTLB for data
accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is
translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical
address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0,
U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded
in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the
accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and
processing switches to the TLB miss exception handling routine. In the TLB miss exception
handling routine, the address translation table in external memory is searched, and the
corresponding physical address and page management information are recorded in the TLB. After
the return from the exception handling routine, the instruction which caused the TLB miss
exception is re-executed.
Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual
memory systems, single virtual memory and multiple virtual memory, either of which can be
selected with the SV bit in MMUCR. In the single virtual memory system, a number of processes
run simultaneously, using virtual address space on an exclusive basis, and the physical address
corresponding to a particular virtual address is uniquely determined. In the multiple virtual
memory system, a number of processes run while sharing the virtual address space, and particular
virtual addresses may be translated into different physical addresses depending on the process.
The only difference between the single virtual memory and multiple virtual memory systems in
terms of operation is in the TLB address comparison method (see section 6.3.3, Address
Translation Method).
Address Space Identifier (ASID): In multiple virtual memory mode, an 8-bit address space
identifier (ASID) is used to distinguish between multiple processes running simultaneously while
sharing the virtual address space. Software can set the 8-bit ASID of the currently executing
process in PTEH in the MMU. The TLB does not have to be purged when processes are switched
by means of ASID.
In single virtual memory mode, ASID is used to provide memory protection for multiple processes
running simultaneously while using the virtual address space on an exclusive basis.
Note: Two or more entries with the same virtual page number (VPN) but different ASID must
not be set in the TLB simultaneously in single virtual memory mode.
Rev. 2.00 May 22, 2009 Page 145 of 1982
REJ09B0256-0200