R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1131

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI is equipped with a 2-channel serial communication interface with built-in FIFO buffers
(Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and
clocked synchronous serial communications.
64-stage FIFO buffers are provided for both transmission and reception, enabling fast, efficient,
and continuous communication.
Channels 0 and 1 of the SCIF have modem control functions (RTS, CTS).
27.1
The SCIF has the following features.
• Asynchronous serial communication mode
• Clocked synchronous serial communication mode
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data transfer formats.
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2 bits
 Parity: Even/odd/none
 Receive error detection: Parity, framing, and overrun errors
 Break detection: A break is detected when a framing error lasts for more than 1 frame
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other LSIs that have a synchronous communication function.
There is a single serial data communication format.
 Data length: 8 bits
 Receive error detection: Overrun errors
Section 27 Serial Communication Interface with FIFO
length at Space 0 (low level). When a framing error occurs, a break can also be detected by
reading the SCIFn_RXD (n = 0, 1) pin level directly from the serial port register
(SCSPTR).
Features
(SCIF)
Section 27 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 May 22, 2009 Page 1061 of 1982
REJ09B0256-0200