R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1164
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 27 Serial Communication Interface with FIFO (SCIF)
27.4
27.4.1
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character and in synchronous mode, in which synchronization is achieved
with clock pulses. For details on asynchronous mode, see section 27.4.2, Operation in
Asynchronous Mode.
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead, and enabling fast and continuous communication to be performed.
SCIF_RTS and SCIF_CTS signals are also provided as modem control signals (channel 0 only).
The serial transfer format is selected using SCSMR, as shown in table 27.5. The SCIF clock
source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits
in SCSCR, as shown in table 27.6.
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
• Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of internal or external clock as SCIF clock source
Clocked Synchronous Mode:
• Data length: Fixed at 8 bits
• Detection of overrun errors during reception
• Choice of internal or external clock as SCIF clock source
Rev. 2.00 May 22, 2009 Page 1094 of 1982
REJ09B0256-0200
determines the transfer format and character length)
data-ready state, and breaks, during reception
When internal clock is selected: The SCIF operates on the baud rate generator clock and can
output a clock with frequency of 16 times the bit rate.
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
When internal clock is selected: The SCIF operates on the baud rate generator clock and a
Operation
Overview
serial clock is output to external devices.
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