R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1528

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 34 Serial Sound Interface (SSI)
34.5
34.5.1
If an overflow occurs during receive DMA operation, the module must be reactivated.
The receive buffer of SSI has 32-bit common register both left channel and right channel. If an
overflow occurs under the condition of control register (SSICR) data-word length (DWL2 to
DWL0) is 32-bit and system-word length (SWL2 to SWL0) is 32-bit, SSI has received the data at
right channel that should be received at left channel.
If an overflow occurs through an overflow error interrupt or overflow error status flag (the OIRQ
bit in SSISR), disable the DMA transfer of the SSI to halt its operation by writing 0 to the EN bit
and DMEN bit in SSICR (then terminate the DMA setting). And clear the overflow status flag by
writing 0 to the OIRQ bit, set the DMA again and transfer restart.
34.5.2
To terminate data transfer while this LSI is used in slave mode, clear the EN bit in SSICR to 0 to
terminate data transfer before the word select signal supply is stopped.
In slave mode, data transfer is terminated if the EN bit (settings for terminating data transfer) is
cleared and the falling edge of the word select signal (SSI_WS) is detected. If the word select
signal supply is stopped before EN bit clear, the falling edge of the word select signal cannot be
detected, and thereby data transfer is not terminated properly.
Rev. 2.00 May 22, 2009 Page 1458 of 1982
REJ09B0256-0200
Usage Note
Restrictions when an Overflow Occurs during Receive DMA Operation
Restrictions for Operation in Slave Mode

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