R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 568

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 PCI Controller (PCIC)
Rev. 2.00 May 22, 2009 Page 498 of 1982
REJ09B0256-0200
Bit
4
3
2
Bit Name
PEDITR
TADIM
MADIM
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Data Parity Error Interrupt for Target PERR
Indicates that the PERR signal has been received
during a target read access (only detected when
PCICMD.PER is set to 1) when the PCIC functions
as a target.
0: PERR detection interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: PERR detection interrupt occurs
[Set condition]
When a PERR detection interrupt occurs.
Target-Abort Detection Interrupt for Master
When the PCIC functions as a master, it has
detected a target-abort, that is, the transaction is
terminated.
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Master-Abort Interrupt for Master
Indicates that the PCIC has terminated a transaction
with a master-abort when the PCIC functions as a
master.
0: Master-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-abort interrupt occurs
[Set condition]
When a master-abort interrupt occurs.