R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 750

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 18 Power-Down Mode
18.4
18.4.1
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of the CPU registers remain unchanged. On-chip peripheral
modules continue to operate, and the clock output on the CLKOUT pin also continues. In sleep
mode, a high level is output to the STATUS1 pin and a low level to the STATUS0 pin.
18.4.2
Sleep mode is canceled by an interrupt (NMI, IRQ/IRL[7:0], or on-chip peripheral module
interrupt) or a reset.
Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save SPC and
SSR to the stack before executing the SLEEP instruction.
(1)
When an NMI, IRQ/IRL[7:0], or on-chip peripheral module interrupt occurs, sleep mode is
canceled and interrupt exception handling is executed. A code indicating the interrupt source is set
in INTEVT.
(2)
Sleep mode is canceled by a power-on reset caused by the RESET pin or watchdog timer overflow
or a manual reset.
Note: If an NMI interrupt is used to cancel sleep mode while the LCD is used, the NMIFL bit in
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Canceling with Interrupt
Canceling with Reset
Moreover, as the LCDC continues to output data stored in the line buffer to the LCD panel
data pin, the LCD display will be stopped if the line buffer becomes empty. Accordingly,
an NMI interrupt should be disabled and the NMIFL bit should be cleared to 0 before the
line buffer becomes empty.
the NMIFCR register is set to 1 by the interrupt. This disables the LCD to access to the
VRAM used for the display data storage (DDR_SDRAM in area 3).
Sleep Mode
Transition to Sleep Mode
Canceling Sleep Mode