R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1127

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. Reset the MDE bit.
(5)
1. Wait for the master event, MST in the master status register.
2. Reset the MST bit after confirming MNR (Master NACK Received).
26.5.2
To set up the master interface to receive a data packet on the I
procedure:
(1)
1. SCL clock generation divider (SCGD) = H'03
2. Clock division ratio (CDF) = H'3
(2)
1. Set master address register to address of slave being accessed and STM1 bit (read mode: 1).
2. Set master control register to H'89
(3)
1. Wait for master event (an interrupt of the MAT and MDR bits in the master status register).
2. Set the master control register to H'88
3. Reset the MAT bit.
Clear MDE after setting the last byte to be transmitted. After the last byte data is transmitted,
MDE is generated. To clear the MDE, you must set the master control register to H'8A.
(Set the force stop control bit).
(SCL frequency of 400 kHz).
(The peripheral clock is 66.7 MHz and the IIC's internal clock IICck is 16.7 MHz.)
(MDBS = 1, MIE = 1, ESG = 1).
(To suspend the data transmission, the master device will hold the SCL low until the MDR bit
is cleared).
If only one byte of data is received, set the master control register to H'8A, meaning that the
stop generation is enabled. This generates a stop on the bus as soon as one byte has been
received.
Wait for End of Transmission
Load Clock Control Register
Load Master Control Register and Address
Wait for Outputting Address
Master Receiver
Rev. 2.00 May 22, 2009 Page 1057 of 1982
2
C bus, follow the following
Section 26 I
2
C Bus Interface (IIC)
REJ09B0256-0200