R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 352

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Interrupt Controller (INTC)
Rev. 2.00 May 22, 2009 Page 282 of 1982
REJ09B0256-0200
Bit
31 to 26 —
25
24
23, 22
21
20
19, 18
17
16
15
14, 13
12
11
10
9
8
7
6
5
4
3
2
Bit Name
SCIF2
USBF
STIF1
STIF0
USBH
GETHER
PCC
ADC
TPU
SIM
SIOF2
SIOF1
LCDC
IIC1
IIC0
SSI3
SSI2
Initial
Value
All 0
0
0
All 0
0
0
All 0
0
0
0
All 0
0
0
0
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
0. The write value should
always be 0
Clears SCIF2 interrupt masking
Clears USBF interrupt masking
0. The write value should
always be 0
Clears STIF1 interrupt masking
Clears STIF0 interrupt masking
0. The write value should
always be 0
Clears GETHER interrupt
masking
Clears PCC interrupt masking
0. The write value should
always be 0
Clears ADC interrupt masking
Clears TPU interrupt masking
Clears SIM interrupt masking
Clears SIOF2 interrupt masking
Clears SIOF1 interrupt masking
The write value should always
be 0
Clears IIC1 interrupt masking
Clears IIC0 interrupt masking
Clears SSI3 interrupt masking
Clears SSI2 interrupt masking
Function
These bits are always read as
These bits are always read as
These bits are always read as
Clears USBH interrupt masking
These bits are always read as
Clears LCDC interrupt masking
This bit is always read as 0.
Description
Clears interrupt
masking for each
peripheral module.
[When writing]
0: Invalid
1: Interrupt mask is
[When reading]
Always 0
cleared

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