R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1284

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
Rev. 2.00 May 22, 2009 Page 1214 of 1982
REJ09B0256-0200
Bit
7 to 5
4 to 0
Bit Name
RFWM[2:0] 000
RFUA[4:0]
00000
Initial
Value
R/W
R/W
R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 12 or more stages
111: Issue a transfer request when 16 stages of the
•
•
Receive FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (empty) to B'10000 (full).
A transfer request to the receive FIFO is issued by
the RDREQE bit in SISTR.
The receive FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
the receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
of the receive FIFO are valid.
receive FIFO are valid.