R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 680

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.4.5
In a repeat mode transfer, a DMA transfer is repeated without specifying the transfer settings
every time before executing a transfer.
Using a repeat mode transfer with the half end function allows a double buffer transfer executed
virtually. Following processing can be executed effectively by using a repeat mode transfer. As an
example, operation of receiving voice data from the VOICE CODEC and compressing it is
explained.
In the following example, processing of compressing 40-word voice data every data reception is
explained. In this case, it is assumed that voice data is received by means of SIOF.
1. DMAC settings
• Set address of the SIOF receive data register in SAR
• Set address of an internal memory data store area in DAR
• Set TCR to H'50 (80 times)
• Satisfy the following settings of CHCR
• Set such as bits TB and TS[2:0] according to use conditions
• Set bits CMS[1:0] and PR[1:0] in DMAOR according to use conditions and set the DME bit to
2. Voice data is received and then transferred by SIOF/DMAC
3. TCR is decreased to half of its initial value and an interrupt is generated
After reading CHCR to confirm that the HE bit is set to 1 by an interrupt processing, clear the HE
bit to 0 and compress 40-word voice data from the address set in DAR.
4. TCR is cleared to 0 and an interrupt is generated
Rev. 2.00 May 22, 2009 Page 610 of 1982
REJ09B0256-0200
Bits RPT[2:0] = B'010: Repeat mode (use DAR as a repeat area)
Bit HIE = B'1: TCR/2 interrupt generated
Bits DM[1:0] = B'01: DAR incremented
Bits SM[1:0] = B'00: SAR fixed
Bit IE = B'1: Interrupt enabled
Bit DE = B'1: DMA transfer enabled
B'1
After reading CHCR to confirm that the TE bit is set to 1 by an interrupt processing, clear the
TE bit to 0 and compress 40-word voice data from the address set in DAR + 40. After this
operation, the value of DARB is copied to DAR in DMAC and initialized, and the value of
TCRB is copied to TCR and initialized to 80.
Repeat Mode Transfer