R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 992

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.76 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether the information for the transmit and receive state reported by bits 17,
16, and 10 to 0 in the E-MAC/E-DMAC status register (EESR) is to be reflected in the TFE or
RFE bit of the corresponding descriptor. The bits in this register correspond to bits 17, 16, and 10
to 0 in EESR. When a bit is cleared to 0, the transmit status (bits 17 and 10 to 8 in EESR) is
reflected in the TFE bit of the transmit descriptor, and the receive status (bits 16 and 7 to 0 in
EESR) is reflected in the RFE bit of the receive descriptor. In this case, the state of a status bit set
to 1 is reflected as the TFE or RFE bit set to 1. When a bit is set to 1, the occurrence of the
corresponding source is not reflected in the descriptor. After this LSI is reset, all bits are cleared to
0.
Rev. 2.00 May 22, 2009 Page 922 of 1982
REJ09B0256-0200
Bit
31 to 18
17
16
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

TABTCE
RABTCE
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
0
28
12


R
R
0
0
27
11


R
R
0
0
R/W
R
R/W
R/W
R/W
DLC
26
10
CE

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
TABT Bit Copy Directive
0: Reflects the TABT bit status in the TFE bit of the
1: Occurrence of the corresponding source is not
RABT Bit Copy Directive
0: Reflects the RABT bit status in the RFE bit of the
1: Occurrence of the corresponding source is not
R/W
25
CD
CE

R
0
9
0
transmit descriptor
reflected in the TFE bit of the transmit descriptor
receive descriptor
reflected in the RFE bit of the receive descriptor
R/W
TRO
24
CE

R
0
8
0
RMAF
R/W
23
CE

R
0
7
0
CEEF
R/W
CE
22

R
0
6
0
CELF
R/W
CE
21

R
0
5
0
R/W
RRF
20
CE

R
0
4
0
RTLF
R/W
CE
19

R
0
3
0
RTSF
R/W
CE
18

R
0
2
0
TABT
R/W
PRE
CE
CE
17
0
1
0
CERF
RABT
R/W
R/W
CE
16
CE
0
0
0