R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1254

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(1)
The reset controller controls resetting of the control register, base counter, and trigger generator.
(2)
The control register has the frequency division register and clock select register.
For details, see section 28.3, Register Descriptions.
(3)
The base counter is a 16-bit CLK (external clock BRG input) synchronization counter.
This counter is used to determine timing of a frequency divided clock when it is generated.
(4)
The trigger generator generates rising-edge/falling-edge triggers for a frequency divided clock,
taking timing according to values of the frequency division register and base counter. The triggers
generate the frequency divided clock.
The trigger generator also switches the output between SCIF2_CLK (external clock input) and the
frequency divided clock.
28.6.2
(1)
1. At the first setting of BSGDL2 after a reset, wait time of one bit period or more is required to
2. After the setting stated in 1 above, wait time of one bit period or more is required at the
Rev. 2.00 May 22, 2009 Page 1184 of 1982
REJ09B0256-0200
ensure the clock settling time.
maximum bit rate (BSGDL2 = 65535) before the value of BSGDL2 is changed again.
Reset controller
Control register
Base counter
Trigger generator
Notes on Frequency Division Register Settings
(Example) Period of one bit when BSGDL2 = 2
3.68 (MHz) × 1/2 × 1/16 = 0.115 (MHz) → 8695 (ns)
Restrictions on the BRG