R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 367

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The priority order of the on-chip modules is specified as desired by setting priority levels from 31
to 0 in INT2PRI0 to INT2PRI14. The priority order of the on-chip modules is set to 0 by a reset.
When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default priority order shown in table
9.7.
Updating of INTPRI and INT2PRI0 to INT2PRI14 should only be carried out when the BL bit in
SR is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority
level setting registers, then clear the BL bit to 0. This will secure the necessary timing internally.
Table 9.7
L: Low
NMI
IRL
H: High
level
input
level
input
(See
table
9.6)
Interrupt Source
IRL[7:4] = LLLL
(H'0)
IRL[3:0] = LLLL
(H'0)
IRL[7:4] = LLLH
(H'1)
IRL[3:0] = LLLH
(H'1)
IRL[7:4] = LLHL
(H'2)
IRL[3:0] = LLHL
(H'2)
IRL[7:4] = LLHH
(H'3)
IRL[3:0] = LLHH
(H'3)
IRL[7:4] = LHLL
(H'4)
IRL[3:0] = LHLL
(H'4)
Interrupt Exception Handling and Priority
INTEVT
Code
H'1C0 16
H'200 15
H'220 14
H'240 13
H'260 12
H'280 11
Interrupt
Priority
MASK/CLEAR
Register
INTMSK2[15]
INTMSKCLR2[15]
INTMSK2[31]
INTMSKCLR2[31]
INTMSK2[14]
INTMSKCLR2[14]
INTMSK2[30]
INTMSKCLR2[30]
INTMSK2[13]
INTMSKCLR2[13]
INTMSK2[29]
INTMSKCLR2[29]
INTMSK2[12]
INTMSKCLR2[12]
INTMSK2[28]
INTMSKCLR2[28]
INTMSK2[11]
INTMSKCLR2[11]
INTMSK2[27]
INTMSKCLR2[27]
Rev. 2.00 May 22, 2009 Page 297 of 1982
Interrupt
Source
Register
Section 9 Interrupt Controller (INTC)
Detail
Source
Register
Priority
in the
Source
REJ09B0256-0200
Default
Priority
High
Low

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