R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1683

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

37.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also section
37.3.20, LCDC User Specified Interrupt Control Register (LDUINTR) and section 37.3.21, LCDC
User Specified Interrupt Line Number Register (LDUINTLNR) for interrupts. Note that
operations by this register setting and LCDC user specified interrupt control register (LDUINTR)
setting are independent.
Initial value:
Bit
15
14
13
R/W:
Bit:
MINT
R/W
Bit Name
MINTEN
FINTEN
VSINTEN
EN
15
0
FINT
R/W
EN
14
0
VSINT
R/W
EN
13
0
Initial Value
0
0
0
VEINT
R/W
12
EN
0
MINTS FINTS VSINTS VEINTS
R/W
11
0
R/W
10
R/W
R/W
R/W
R/W
0
R/W
9
0
Description
Memory Access Interrupt Enable
Enables or disables an interrupt generation at the
start point of each vertical retrace line period for
VRAM access by LCDC.
0: Disables an interrupt generation at the start point
1: Enables an interrupt generation at the start point
Frame End Interrupt Enable
Enables or disables the generation of an interrupt
after the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last
1: Enables an interrupt generation when the last
Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at
the start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsync is disabled
1: Interrupt at the start point of the Vsync is enabled
of each vertical retrace line period for VRAM
access
of each vertical retrace line period for VRAM
access
pixel of the frame is output
pixel of the frame is output
R/W
8
0

R
7
0
Rev. 2.00 May 22, 2009 Page 1613 of 1982

R
6
0

R
Section 37 LCD Controller (LCDC)
5
0

R
4
0

R
3
0
REJ09B0256-0200

R
2
0

R
1
0

R
0
0