R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 523

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 13.1 is a block diagram of the PCIC.
The PCIC comprises two blocks: the PCI bus interface and SuperHyway bus interface block.
The PCI bus interface block comprises the PCI configuration register, local register, PCI master,
and PCI target controller.
The functions of the PCI bus interface are transaction control on the PCI local bus.
The SuperHyway bus interface block comprises the control register (PCIECR) and the data FIFO.
The functions of the SuperHyway bus interface are access translation between the PCI bus
interface and the CPU or DMAC via SuperHyway bus.
The interrupt controller requests interrupt request to the INTC of this LSI.
SHck
(SuperHyway bus clock)
SuperHyway bus
[Legend]
PCIECR: PCI enable control register
PCIC
SuperHyway bus
Interrupt control
Figure 13.1 PCIC Block Diagram
32-Byte
32-Byte
Data FIFO
Data FIFO
(2 planes)
(2 planes)
Interface
PCIECR
2
2
PCI standard signal
PCI local bus
Target control
Configuration/local
Master control
Register control
(PCI bus access control)
PCI bus Interface
register
Rev. 2.00 May 22, 2009 Page 453 of 1982
PCIRESET
Section 13 PCI Controller (PCIC)
PCICLK
(PCI bus clock)
REJ09B0256-0200
Host/normal
MODE6