R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1117

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Consequently, when receiving data continuously, be sure to clear the status of MDR and SDR
after reading the receive data register.
(2)
If the MDE or SDE status bits are still set data in the transmit data register is to be transmitted on
the I
bits are reset. The MDE or SDE status bit being set indicates that the data currently held in the
Transmit Data Register has already been transmitted on the I
The software must clear this status bit when it writes to the transmit data register which is ready to
transmit subsequent data bytes. This is not required for the first byte of data to be transmitted on
the bus.
(3)
When the master loses arbitration, the MAL bit (of the master status register) is set and the MIE
bit (of the master control register) is reset. At this point, master mode is invalid and the I
interface enters the slave mode. When master operation is restarted, data transfer from the master
begins after the MAL bit has been cleared.
(4)
The SAR status bit is set when the slave identifies its address on the I
slave interface forces the SCL line low until the SAR status bit is reset.
This is particularly important when a slave transmit is about to take place on the bus, and the slave
will transmit the data from the transmit data register. The software responds to the SAR status by
writing the required data into the transmit data register and then resetting the SAR status bit. This
allows the slave interface to continue the access.
When the slave is about to receive data, the software may be reading data loaded in a previous
access from the receive data register. In this case the valid data still held in the receive data
register is overwritten. However, this is avoided using the SAR status bit. After the software has
read data in the receive data register, reset the SAR bit (if it is set). Then overwriting the receive
data register is avoided.
2
C bus by the slave or master, the SCL line must be held low until the MDE and SDE status
MDE and SDE
MAL
SAR
Rev. 2.00 May 22, 2009 Page 1047 of 1982
2
C bus.
Section 26 I
2
C bus. At this point the
2
C Bus Interface (IIC)
REJ09B0256-0200
2
C bus