R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1672

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 37 LCD Controller (LCDC)
Notes: 1. The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation
Rev. 2.00 May 22, 2009 Page 1602 of 1982
REJ09B0256-0200
Bit
31 to 28 
27, 26
25 to 4
3 to 0
2. When the hardware rotation function is used (ROT = 1), set the upper-left address of
Bit Name

SAU[25:4] All 0

function is not used. Write 0 to the lower nine bits. When using the hardware rotation
function, set the LDSARU value so that the upper-left address of the image is aligned
with the 512-byte boundary.
the image which can be calculated from the display image size in this register. The
equation below shows how to calculate the LDSARU value when the image size is 240
× 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but
from the memory size of the image to be displayed. Note that LDLAOR must be a
binary exponential at least as large as the horizontal width of the image. Calculate
backwards using the LDSARU value (LDSARU − 256 (LDLAOR value) × (320 − 1)) to
ensure that the upper-left address of the image is aligned with the 512-byte boundary.
LDSARU = (upper-left address of image) + 256 (LDLAOR value) × 319 (line)
Initial Value
All 0
All 1
All 0
R/W
R
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Upper Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
Reserved
These bits are always read as 0. The write value
should always be 0.