R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 380

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
INTMSK0/INTMSK1 and INTMSKCLR0/INTMSKCLR1 and reading from
INTMSK0/INTMSK1 should be consecutively executed.
9.7.2
When switching the IRQ7/IRL7 to IRQ0/IRL0 pin function, it is possible that the INTC may hold
an interrupt by mistake. Therefore, to prevent detecting unintentional interrupts, mask both all
IRQ and IRL interrupts and then switch the IRQ7/IRL7 to IRQ0/IRL0 pin function.
Table 9.9
9.7.3
Clearing procedure of the interrupt held in the INTC is as follows
• To clear IRL interrupt requests
• To clear IRQ level-sense interrupt requests
Rev. 2.00 May 22, 2009 Page 310 of 1982
REJ09B0256-0200
Sequence ITEM
1
2
3
4
To clear an IRL interrupt request from the IRQ3/IRL3 to IRQ0/IRL0 pins, write 1 to the IM10
bit in INTMSK1, and to clear an IRL interrupt request from the IRQ7/IRL7 to IRQ4/IRL4
pins, write 1 to the IM11 bit in INTMSK1. The IRL interrupt requests detected by the INTC is
not cleared even if each of the corresponding interrupt level is masked by setting INTMSK2.
To clear an IRQ level-sense interrupt request from the IRQ7/IRL7 to IRQ0/IRL0 pins, write 1
to the corresponding mask bit (IM07 to IM00) in INTMSK0.
The IRQ interrupt requests detected by the INTC is not cleared even if 0 is written to a
corresponding bit in INTPRI. The IRQ interrupt sources detected by the INTC (be cleared)
Notes on Setting IRQ7/IRL7 to IRQ0/IRL0 Pin Function
To Clear IRQ and IRL Interrupt Requests
IRL interrupt request and IRQ interrupt
request masking
IRQ7/IRL7 to IRQ4/IRL4 pins setting to
IRL7 to IRL4 interrupt request input
IRQ7/IRL7 to IRQ0/IRL0 pins setting to
IRL or IRQ interrupt request input
IRL and IRQ interrupt detection start
Switching Sequence of IRQ7/IRL7 to IRQ0/IRL0 Pin Function
PROCEDURE
Write 1 to all bits in INTMSK0 and
INTMSK1
Write 010 to the PTSEL3[14:12] bits and
the PTSEL3[2:0] bits in PSEL3 of GPIO
Write 00 to the PL3MD[1:0], PL1MD[1:0],
PL0MD[1:0] bits in PLCR
Set the IRLM[1:0] bit in ICR0
Write 1 to the corresponding bit in
INTMSKCLR0 and INTMSKCLR1