R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1026

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
(4)
The E-DMAC controls the transmit and receive descriptor addresses in memory and the
processing priority by using the following registers.
1. Registers related to a transmit descriptor
• TDLAR: Address of the start descriptor in a list of transmit descriptors.
• TDFAR: Address of the transmit descriptor to be processed
• TDFXR: Address of the transmit descriptor that finished processing (set by a write-back
• TDFFR (DL bit): Indicates whether the TDLE value of the transmit descriptor specified by
2. Registers related to receive descriptor:
• RDLAR: Address of the start descriptor in a list of receive descriptors.
• RDFAR: Address of the receive descriptor to be processed
• RDFXR: Address of the receive descriptor that finished processing (set by a write-back
• RDFFR (DL bit): Indicates whether the RDLE value of the receive descriptor specified by
Transmit descriptors and receive descriptors have a ring structure. When the TDLE (RDLE) value
of the processed transmit (receive) descriptor is 0, the next descriptor will be processed. The next
descriptor is the transmit (receive) descriptor at the address obtained by adding the processed
transmit (receive) descriptor address to the descriptor length specified by the DL bit in EDMR.
When the TDLE (RDLE) value of the processed transmit (receive) descriptor is 1, the transmit
descriptor indicated by TDLAR (RDLAR) will be processed next. Figure 23.7 shows the
relationship between the transmit/receive descriptor ring and read pointer.
The transmit descriptor list must be large enough to point to five or more transmit frames. If four
or less transmit frames are pointed to in a list, E-DMAC operation is not guaranteed. Accordingly,
do not set that all the transmit descriptors in a ring are used by four or less descriptors. The receive
descriptor list does not have this restriction. For example, one receive frame can use all receive
descriptors in a list.
In the initial setting, the start address of a descriptor list must be set to TDLAR (RDLAR) and
TDFAR (RDFAR), and the end descriptor address of the descriptor list to TDFXR (RDFXR) by
the software.
The E-DMAC updates TDFAR (RDFAR), TDFXR (RDFXR) and the DL bit in TDFFR (DL bit in
RDFFR) each time a descriptor is processed.
Rev. 2.00 May 22, 2009 Page 956 of 1982
REJ09B0256-0200
operation) last
TDFXR is 1 or not.
operation) last
RDFXR is 1 or not.
Descriptor Pointer