R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 44

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 11.38 Byte-Control SRAM Basic Read Cycle
Figure 11.39 Wait Cycles between Access Cycles ..................................................................... 405
Figure 11.40 Arbitration Sequence............................................................................................. 407
Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.1 DDRIF Block Diagram ........................................................................................... 412
Figure 12.2 Data Alignment in DDR-SDRAM and DDRIF....................................................... 416
Figure 12.3 Relationship between Write Values in SDMR and Output Signals to Memory
Figure 12.4 DDR-SDRAM Access............................................................................................. 432
Figure 12.5 Basic DDRIF Timing
Figure 12.6 Basic DDRIF Timing
Figure 12.7 Basic DDRIF Timing
Figure 12.8 Basic DDRIF Timing
Figure 12.9 Basic DDRIF Timing (4 Burst Read: 32 Bytes; Without Auto-Precharge)............. 444
Figure 12.10 Basic DDRIF Timing (4 Burst Write: 32 Bytes; Without Auto-Precharge).......... 445
Figure 12.11 Basic DDRIF Timing
Figure 12.12 Basic DDRIF Timing (Mode Register Set (MRS)) ............................................... 447
Figure 12.13 Basic DDRIF Timing
Figure 12.14 Basic DDRIF Timing (Self-Refresh Entry from IDLE (REFS)/
Section 13 PCI Controller (PCIC)
Figure 13.1 PCIC Block Diagram .............................................................................................. 453
Figure 13.2 SuperHyway Bus to PCI Local Bus Access ............................................................ 532
Figure 13.3 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.4 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.5 SuperHyway Bus to PCI Local Bus Address Translation
Figure 13.6 SuperHyway Bus to PCI Local Bus Address Translation (PCI I/O) ....................... 535
Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Local bus
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Pins.......................................................................................................................... 430
(1 Burst Read: 1, 2, 4, or 8 Bytes; Without Auto-Precharge).................................. 440
(1 Burst Write: 1, 2, 4, or 8 Bytes; Without Auto-Precharge)................................. 441
(1 Burst Read: 1, 2, 4, or 8 Bytes; With Auto-Precharge)....................................... 442
(1 Burst Write: 1, 2, 4, or 8 Bytes; With Auto-Precharge)...................................... 443
(PCI Memory Space 0)............................................................................................ 533
(PCI Memory Space 1)............................................................................................ 534
(PCI Memory Space 2)............................................................................................ 534
(Non-Byte Swapping: TBS = 0).............................................................................. 537
(One Internal Wait + One External Wait).............................................................. 403
(Precharge all Banks (PREALL) to Bank Activate (ACT)) .................................. 446
(Auto-Refresh (REFA) Enter/Exit to Bank Activate (ACT)) ................................ 448
Self-Refresh Exit (REFSX) to Any Command Input) ........................................... 449