R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 821

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21.2
Table 21.2 shows the CMT register configuration. Table 21.3 shows the register state in each
operating mode.
Table 21.1 Register Configuration
Note:
Register Name
Compare match timer start register
Compare match timer control/status
register_0
Compare match timer counter_0
Compare match timer constant
register_0
Compare match timer control/status
register_1
Compare match timer counter_1
Compare match timer constant
register_1
Compare match timer control/status
register_2
Compare match timer counter_2
Compare match timer constant
register_2
Compare match timer control/status
register_3
Compare match timer counter_3
Compare match timer constant
register_3
Compare match timer control/status
register_4
Compare match timer counter_4
Compare match timer constant
register_4
*
Register Descriptions
P4 addresses are used when area P4 in the virtual address space is used, and area 7
addresses are used when accessing the register through area 7 in the physical address
space using the TLB.
Abbreviation R/W
CMSTR
CMCSR_0
CMCNT_0
CMCOR_0
CMCSR_1
CMCNT_1
CMCOR_1
CMCSR_2
CMCNT_2
CMCOR_2
CMCSR_3
CMCNT_3
CMCOR_3
CMCSR_4
CMCNT_4
CMCOR_4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 2.00 May 22, 2009 Page 751 of 1982
Area P4
Address*
H'FFE2 0000 H'1FE2 0000 16
H'FFE2 0010 H'1FE2 0010 16
H'FF20 0014 H'1F20 0014 32
H'FF20 0018 H'1F20 0018 32
H'FFE2 0020 H'1FE2 0020 16
H'FF20 0024 H'1F20 0024 32
H'FF20 0028 H'1F20 0028 32
H'FFE2 0030 H'1FE2 0030 16
H'FF20 0034 H'1F20 0034 32
H'FF20 0038 H'1F20 0038 32
H'FFE2 0040 H'1FE2 0040 16
H'FF20 0044 H'1F20 0044 32
H'FF20 0048 H'1F20 0048 32
H'FFE2 0050 H'1FE2 0050 16
H'FF20 0054 H'1F20 0054 32
H'FF20 0058 H'1F20 0058 32
Section 21 Compare Match Timer (CMT)
Area 7
Address*
REJ09B0256-0200
Access
Size

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