R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1017

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When one transmit frame is divided into three parts or more with transmit descriptors, the E-
DMAC performs the following write-back operation:
• A write-back operation is performed for a transmit descriptor including information for the
• A write-back operation is not performed for a transmit descriptor for the middle of the frame
However, TFE (transmit frame error occurrence) or TFS (transmit frame status) is written only to
a transmit descriptor including information for the end of the frame (TFP = 01 or 11) by a write-
back operation.
Before changing a transmit descriptor with the software, make sure that a write-back operation has
been performed (TACT = 0) for the transmit descriptor including information for the end of the
frame (TFP = 01 or 11) to avoid overwriting (re-setting) an unprocessed transmit descriptor.
(2)
Figure 23.4 shows the relationship between a receive descriptor and receive buffer.
The data of a receive descriptor consists of RD0, RD1, RD2, and padding data in groups of 32 bits
from top to end. The length of padding data is determined according to the descriptor length
specified by the DL0 and DL1 bits in EDMR.
RD0 indicates whether the receive descriptor is valid or invalid, and information about descriptor
configuration and status. RD1 indicates the length of data that can be received in the receive buffer
specified by the descriptor (RBL) and the length of the received frame data (RDL). RD2 indicates
the start address of the receive buffer for storing receive data (RBA).
Depending on the descriptor specification, one receive descriptor can specify the storing of all
receive data of one frame in a receive buffer (single-frame/single-buffer) or multiple descriptors
can specify the storing of the receive data of one frame in receive buffers (single-frame/multi-
buffer). As an example of single-frame/multi-buffer operation, suppose that a row of multiple
descriptors (descriptor list) is prepared, RBL of each descriptor is 500 bytes, and a 1514-byte
Ethernet frame is received. In such a case, the received Ethernet frame is transferred sequentially
to buffers, 500 bytes for each buffer, starting with the first descriptor. Only the last 14 bytes are
transferred to the fourth buffer. When a frame longer than RBL of a descriptor is received, the E-
DMAC transfers the remaining data to the receive buffer by using the subsequent descriptors. As
an example of efficient single-frame/multi-buffer operation, information items on different
processing layers in an Ethernet frame can be separated from each other by using different buffers.
For example, the destination address, transmit source address, and type field data in an Ethernet
start of the transmit frame (TFP = 10 or 11) and for a transmit descriptor including information
for the end of the frame (TFP = 01 or 11).
(TFP = 00).
Receive Descriptor
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 947 of 1982
REJ09B0256-0200