R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1278

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
Rev. 2.00 May 22, 2009 Page 1208 of 1982
REJ09B0256-0200
Bit
5
4
Bit Name
SAERR
FSERR
Initial
Value
0
0
R/W
R/W
R/W
Description
Slot Assign Error
0: Indicates that no slot assign error occurs
1: Indicates that a slot assign error occurs
A slot assign error occurs when the specifications in
SITDAR, SIRDAR, and SICDAR overlap.
If a slot assign error occurs, the SIOF does not transmit
data to the SIOF_TXD pin and does not receive data
from the SIOF_RXD pin. Note that the SIOF does not
clear the TXE bit or RXE bit in SICTR at a slot assign
error.
•
•
•
Frame Synchronization Error
0: Indicates that no frame synchronization error occurs
1: Indicates that a frame synchronization error occurs
A frame synchronization error occurs when the next
frame synchronization timing appears before the
previous data or control data transfers have been
completed.
If a frame synchronization error occurs, the SIOF
performs transmission or reception for slots that can be
transferred.
•
•
•
This bit is valid when the TXE bit or RXE bit in
SICTR is 1.
When 1 is written to this bit, the contents are
cleared.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the TXE or RXE bit in SICTR
is 1.
When 1 is written to this bit, the contents are
cleared. Writing 0 to this bit is invalid.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.