R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1342

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
Table 30.5 Example of Bit Rates (bits/s) for SCBRR Settings
Note: The bit rate is a value that is rounded off below the decimal point.
30.4.5
(1)
Prior to data transmission and reception, the following procedure should be used to initialize the
smart card interface. Initialization is also necessary when switching from transmit mode to receive
mode, and when switching from receive mode to transmit mode. An example of the initialization
process is shown in the flowchart of figure 30.4.
Step (1) to step (7) of figure 30.4 correspond to the following operation.
1. Clear the TE and RE bits in the serial control register (SCSCR) to 0.
2. Clear the error flags PER, ORER, ERS, and WAIT_ER in the serial status register (SCSSR) to
3. Set the parity bit (O/E bit) in the serial mode register (SCSMR).
4. Set the LCB, PB, SMIF, SDIR, and SINV bits in the smart card mode register (SCSCMR).
5. Set the value corresponding to the bit rate to the bit rate register (SCBRR).
6. Set the clock source select bits (CKE[1] and CKE[0] bits) in the serial control register
7. After waiting at least 1 etu, set the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits in SCSCR.
Rev. 2.00 May 22, 2009 Page 1272 of 1982
REJ09B0256-0200
SCBRR Setting
7
6
5
4
0.
(SCSCR). At this time, the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits should be cleared to 0.
If the CKE[0] bit is set to 1, a clock signal is output from the SIM_CLK pin.
Except for self-check, the TE bit and RE bit should not be set simultaneously.
Initialization
Data Transmit/Receive Operation
(Pck0 = 66.6 MHz, SCSMPL = 371)
SCK Frequency (MHz)
4.16
4.76
5.55
6.66
Bit Rate (bits/s)
11190
12788
14919
17903