R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1008

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.4
The GETHER consists of the following three function units:
• DMA transfer controller (E-DMAC):
• MAC controller (E-MAC):
• Transfer Switching Unit (TSU): Transfer processing between port 0 and port 1, and CAM
Using its direct memory access (DMA) function, the E-DMAC performs DMA transfer of frame
data between a user-specified Ethernet frame transmission/reception data storage destination
(accessible memory space: transmit buffer/receive buffer) and the transmit/receive FIFO in the E-
DMAC. The user cannot read and write data from and to the transmit/receive FIFO directly via the
CPU.
To enable the E-DMAC to perform DMA transfer, information (data) including a transmit/receive
data storage address and so forth, referred to as a descriptor, is required. The E-DMAC reads
transmit data from the transmit buffer or writes receive data to the receive buffer according to the
descriptor information. By arranging multiple descriptors as a descriptor row (list) (to be placed in
a readable/writable memory space), multiple Ethernet frames can be transmitted or received
continuously.
The E-DMAC consists of two systems: one for port 0 and the other for port 1, and both operate
independently for transmission and reception.
The E-MAC constructs an Ethernet frame using the data written to the transmit FIFO and
transmits the frame to the GMII/MII/RMII. It also performs a CRC check of an Ethernet frame
received from the GMII/MII/RMII and deconstructs the frame to write to the receive FIFO. The E-
MAC supports three formats MII, GMII and RMII for interface to the PHI-LSI connected
externally to this LSI.
The E-MAC consists of two controllers: E-MAC0 for port 0 and E-MAC1 for port 1, which
correspond to E-DMAC0 and E-DMAC1 respectively.
The TSU performs Ethernet frame data transfer between the E-MAC0 and E-MAC1. The TSU,
which is placed between the E-DMAC and E-MAC, references the CAM entry table to select one
of the following tasks according to the Ethernet frame destination address (DA) input to the E-
MAC.
Rev. 2.00 May 22, 2009 Page 938 of 1982
REJ09B0256-0200
the memory and the transmit/receive FIFO
transmit/receive FIFO and the GMII/MII/RMII
processing
Operation
Transmission/reception processing between the
DMA transfer between the transmit/receive buffer in