R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1352

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 30 SIM Card Module (SIM)
(b) Retransmission when the smart card interface is in transmit mode (T = 0)
1. After completion of transmission of one frame, if an error signal is returned from the receive
2. In T = 0 mode, the TEND bit in SCSSR is not set for a frame when an error signal indicating
3. If no error signal is returned from the receive side, the ERS bit in SCSSR is not set.
4. If no error signal is returned from the receive side, it is assumed that transmission of one
Rev. 2.00 May 22, 2009 Page 1282 of 1982
REJ09B0256-0200
Figure 30.9 shows retransmit operations when the smart card interface is in transmit mode.
Step (1) to step (4) of figure 30.9 correspond to the following operation
side, the ERS bit in SCSSR is set to 1. If the RIE bit in SCSCR is set to enable, an ERI request
is issued. The ERS bit in SCSSR should be cleared to 0 before the sampling timing for the next
parity bit.
an error is received.
frame, including retransmission, is completed, and the TEND bit in SCSSR is set to 1. At this
time, if the TIE bit in SCSCR is set to enable, a TEI interrupt request is issued.
TDRE
TEND
ERS
Transmission from SCTDR to SCTSR
Ds
D0 D1 D2 D3 D4 D5 D6 D7 DP
nth transmit frame
Figure 30.9 Retransmit Standby Mode (Clock Stopped)
when Smart Card Interface is in Transmit Mode
(1)
DE
(2)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 DP
Retransmit frame
(4)
(3)
Transmisson from SCTDR to SCTSR
(DE)
Ds
(n+1) th transmit frame
D0 D1 D2 D3 D4

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