R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1576

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 36 USB Function Controller (USBF)
36.3.1
IFR0 is an interrupt flag register for EP0i, EP1, EP2, bus reset, and setup command reception.
When each flag is set to 1 and interrupt is enabled in the corresponding bit of IER0, an interrupt
request (USBF10 or USB11) specified by the corresponding bit in ISR0 is issued to INTC.
Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear
bits, access the register so that 0 should be only to the bits for the interrupt sources to be cleared
and that 1 should be written to the other bits. Do not use a bit field declaration of the C language
to clear bits.
EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2,
respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Rev. 2.00 May 22, 2009 Page 1506 of 1982
REJ09B0256-0200
Bit
31 to 8 
7
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name
BRST
Interrupt Flag Register 0 (IFR0)
—
—
—
—
R
R
30
14
—
—
—
—
R
R
Initial Value
Undefined
0
29
13
—
—
—
—
R
R
28
12
—
—
—
—
R
R
27
11
—
—
—
—
R
R
R/W Description
R
R/W Bus Reset
26
10
—
—
—
—
R
R
Reserved
These bits are always read as undefined value. Write
value should always be 0.
[Setting condition]
When a bus reset signal is detected on the USB bus.
[Clearing conditions]
•
•
25
—
—
—
—
R
R
9
When reset
When 0 is written to by CPU
24
—
—
—
—
R
R
8
BRST
R/W
23
—
—
R
7
0
FULL
EP1
22
—
—
R
R
6
0
R/W
EP2
21
TR
—
—
R
5
0
EMPTY
EP2
20
—
—
R
R
4
1
SETUP
R/W
19
—
—
R
TS
3
0
EP0O
R/W
18
TS
—
—
R
2
0
R/W
EP0I
17
TR
—
—
R
1
0
EP0I
R/W
16
TS
—
—
R
0
0