R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1114

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 26 I
Note: CDF must be set so that the clock frequency (IICck) is lower than 20 MHz.
Rev. 2.00 May 22, 2009 Page 1044 of 1982
REJ09B0256-0200
Bit
7 to 2
1, 0
2
C Bus Interface (IIC)
Bit Name
SCGD
CDF
Initial Value
All 0
All 0
R/W
R/W
R/W
Description
SCL Clock Generation Divider
When operating in master mode, the SCL
clock is generated from the internal clock using
SCGD as the ratio. The slave will also operate
on the clock generated from the internal clock
when SCL is held low to hold the bus up when
an overflow occurs. SCGD must be specified in
both master and slave modes. The formula
expressing the relationship is:
Equation 2 SCL rate calculation
Suggested settings for CDF and SCGD for
various CPU speeds and the two I
speeds are given in table 26.4.
Clock Division Factor
The internal clock used in most blocks in the
I
internal I
peripheral clock using the CDF as the division
ratio:
Equation 1 I
calculation
The minimum time to ensure adequate setup
and hold times on the SDA line relative to the
SCL line on the bus.
The clock frequency is to ensure that the glitch
filtering will operate with glitches of up to 50 ns
as described in the fast mode I
2
C module is a divided peripheral clock. The
2
SCLfreq = IICck / (20 + (SCGD * 8))
IICck: I
IICck = Pck0 / (1 + CDF)
Pck0: Peripheral clock
C clock is generated from the
2
C internal clock frequency
2
C internal clock frequency
2
C specification.
2
C bus