R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1023

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(c)
RD2 indicates the start address of the corresponding receive buffer. Set the start address of a
receive buffer with a 32-byte boundary.
The E-DMAC performs DMAtransfer for a receive frame from the address specified by RBA
(receive buffer address) to the receive buffer in 32-byte units. RBL (receive buffer length) must be
set to be an integral multiple of 32 bytes.
If data to be transferred is less than 32 bytes, invalid data will be written to.
[Example]
When the receive frame length is 170 bytes and the required receive buffer capacity is 192 bytes
(32 bytes × 6), the sixth DMA-transfer causes invalid data to be written to the receive buffer (In
the 32-byte DMA data, the former 10 bytes are valid and the latter 22 bytes are invalid).
Padding of the value 0 can be inserted into only one position in the receive frame by setting
RPADIR. The padding size can be selected from 1 byte to 31 bytes in byte units. When padding is
inserted into a receive frame, a receive buffer area equal to the total of "receive frame length and
padding size" is required. RPADIR setting is valid for all receive frames.
RFE (receive frame error occurrence), PV (padding insertion), RFS (receive frame status) and
RFS (receive frame status) are only set in the receive descriptor including information for the end
of the frame (TFP = 01 or 11) by a write-back operation.
Before re-setting a receive descriptor with the software, completion of a write-back operation for
the receive descriptor (RACT = 0) must be confirmed to avoid rewriting to (and re-setting) an
unprocessed receive descriptor.
Bit
31 to 0
Receive Descriptor 2 (RD2)
Bit
Name
RBA
Initial
Value
All 0
R/W
R/W
Description
Receive Buffer Start Address
These bits set the start address of the corresponding
receive buffer with a 32-byte boundary.
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 953 of 1982
REJ09B0256-0200