R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 184

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Exception Handling
5.5.2
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions—general
illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot
FPU disable exception, and unconditional trap exception—are detected in the process of
instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.2.
Rev. 2.00 May 22, 2009 Page 114 of 1982
REJ09B0256-0200
Pipeline flow:
Order of detection:
Order of exception handling:
Exception Source Acceptance
Instruction n
Instruction n + 1
Instruction n + 2
Instruction n + 3
General illegal instruction exception (instruction n + 1) and
TLB miss (instruction n + 2) are detected simultaneously
TLB miss (instruction n)
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n + 1)
Re-execution of instruction n + 1
TLB miss (instruction n + 2)
Re-execution of instruction n + 2
Execution of instruction n + 3
Figure 5.2 Example of General Exception Acceptance Order
I1
I1
I1
I2
I2
ID
ID
I1
I2
TLB miss (instruction access)
General illegal instruction exception
E1
E1
ID
I2
E1
E2
E2
ID
TLB miss (data access)
Program order
E3
E3
E2
E1 E2
1
2
3
4
WB
WB
E3
WB
E3
WB
[Legend]
I1, I2 :
ID :
E1, E2, E3 : Instruction execution
(E2, E3:
WB :
Instruction fetch
Instruction decode
Write-back
Memory access)