R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1120

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 26 I
26.4.7
Description is given below on the 10-bit address transfer format supported in master mode.
This format has three transfer methods as the 7-bit address transfer format.
Figure 26.6 shows the data transmit format. The set value in the master address register is output
in one byte following the first START condition (S). The value set in the transmit data register
(TXD) is transmitted as a slave address in the second byte. Data on and after the third byte is
transferred in the same way as the 7-bit address data.
Figure 26.7 shows the data receive format. Two bytes of an address is transmitted a repeated
START in the same way as in the data transmit format. Then, repeated START condition (Sr) is
transmitted and the value set in the address register is output. At this time, STM1 must be set to 1
(receive mode). Data is transferred in the same way as in the 7-bit address data receive format.
Rev. 2.00 May 22, 2009 Page 1050 of 1982
REJ09B0256-0200
Notes: 1. Tramsfer dorection of data and acknowledge bits depends on R/W bits.
S
SLAVE ADDRESS
S
2. Repeated START condition: Tramsfer is started whrn the I2C_SDL signal is driven high and the I2C_SDA signal is
driven low.
10-Bit Address Format
SLAVE ADDRESS
2
1 1 1 1 0 X X
C Bus Interface (IIC)
1st Byte, 7 Bits
Figure 26.5 Combination Transfer Format of Master Transfer
Read or Write
Figure 26.6 10-Bit Address Data Transmit Format
R/W
0(Write)
R/W
A
DATA
A1
(n BYTES
+ ACK)*
SLAVE ADDRESS
A/A
2nd Byte
Sr = Repeated start condition
Sr
SLAVE ADDRESS
A2
DATA
(n Bytes + ACKNOWLEDGE)
Read or Write
Data transferred
R/W
Direction pf transfer
may change at this point
A
DATA
A
DATA
(n BYTES
+ ACK)*
A/A
A/A
P
P