R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1330

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
30.3.7
SCRSR is a register that receives serial data.
The smart card interface receives serial data input from the SIM_RXD pin in order, from the LSB
or MSB, and sets it in SCRSR, converting it to parallel data. When reception of one byte of data is
completed, the data is automatically transferred to SCRDR. The CPU or DMAC cannot directly
read from or write to SCRSR.
30.3.8
SCRDR is an 8-bit read-only register that stores received serial data.
When reception of one byte of serial data is completed, the smart card interface transfers the
received serial data from the receive shift register (SCRSR) to SCRDR for storage, and completes
the receive operation. Thereafter, SCRSR can receive data. In this way, SCRSR and SCRDR
constitute a double buffer, enabling continuous reception of data. SCRDR cannot be written to by
the CPU or DMAC.
Rev. 2.00 May 22, 2009 Page 1260 of 1982
REJ09B0256-0200
Bit
0
Bit
7 to 0
Bit Name

Bit Name
SCRD[7:0] All 0
Receive Shift Register (SCRSR)
Receive Data Register (SCRDR)
Initial
Value
0
Initial value:
Initial
Value
R/W:
Bit:
R/W
R
R
R/W
R
0
7
Description
Reserved
This bit is always read as 0. The write value should always
be 0.
R
6
0
Description
Receive Data
Store received serial data.
R
5
0
SCRD[7:0]
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0