R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 644

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.1
SAR is 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary
must be set for the source address value. The initial value is undefined.
Rev. 2.00 May 22, 2009 Page 574 of 1982
REJ09B0256-0200
2
3
0, 1
2, 3
4, 5
Channel
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Source Address Registers (SAR0 to SAR5)
Abbreviation
SARB1
DARB1
TCRB1
SARB2
DARB2
TCRB2
SARB3
DARB3
TCRB3
DMARS0
DMARS1
DMARS2
R/W
R/W
31
—
15
—
R/W
R/W
30
—
14
—
R/W
R/W
29
—
13
—
R/W
R/W
28
—
12
—
Power-on Reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
H'0000
H'0000
H'0000
R/W
R/W
27
—
11
—
R/W
R/W
26
—
10
—
R/W
R/W
25
—
—
9
Undefined
Undefined
Undefined
H'0000
H'0000
H'0000
Manual Reset Sleep
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
R/W
24
—
—
8
SAR
SAR
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
Stand by
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0