R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 887

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
3
2
1
0
Bit Name
PHYI
LCHNG
MPD
ICD
Initial
Value
0
0
0
0
R/W
R
R/W
R/W
R/W
Description
ET_PHY-INT Interrupt
Indicates the state of the ET_PHY-INT pin input from
the PHY-LSI.
0: ET_PHY-INT pin is not asserted
1: ET_PHY-INT pin is asserted
The signal polarity of the ET_PHY-INT pin can be set
by PIPR.
Link Signal Change
Indicates that the ET_LNKSTA signal input from the
PHY-LSI has changed from high to low or low to high.
However, signal changes may be detected at the timing
at which the ET_LNKSTA function was selected using
PACR of the GPIO.
To check the current Link state, refer to the LMON bit in
the PHY status register (PSR).
0: Change in the ET_LNKSTA signal has not been
1: Change in the ET_LNKSTA signal has been
Magic Packet Detection
Indicates that a Magic Packet has been detected on the
line.
0: Magic Packet has not been detected
1: Magic Packet has been detected
Illegal Carrier Detection
Indicates that the PHY-LSI has detected an illegal
carrier on the line. If a change in the signal input from
the PHY-LSI occurs in a period shorter than the
software recognition period, the correct information may
not be obtained. Refer to the timing specification for the
PHY-LSI used.
0: PHY-LSI has not detected an illegal carrier on the
1: PHY-LSI has detected an illegal carrier on the line
detected
detected (high to low or low to high)
line
Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 2.00 May 22, 2009 Page 817 of 1982
REJ09B0256-0200

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