R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 320

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
Interrupt priorities should be determined by setting a value from H'F to H'1 to each 4-bit field. If
the value is larger, the priority is higher. When the value of H'0 is set to a field, a corresponding
interrupt is masked (initial value).
9.3.4
INTREQ is a 32-bit readable and writable with conditions register that indicates which IRQ [n] (n
= 0 to 7) interrupt is requested to the INTC.
Even if interrupts are masked by INTPRI and INTMSK0, the INTREQ bits are not affected.
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 250 of 1982
REJ09B0256-0200
Bit
31 to 28 IP0
27 to 24 IP1
23 to 20 IP2
19 to 16 IP3
15 to 12 IP4
11 to 8
7 to 4
3 to 0
R/W:
R/W:
Bit:
Bit:
Interrupt Source Register (INTREQ)
Bit Name
IP5
IP6
IP7
R/W
IR0
31
15
−
R
0
0
R/W
IR1
30
14
−
R
0
0
R/W
Initial
Value
H'0
H'0
H'0
H'0
H'0
H'0
H'0
H'0
IR2
29
13
−
R
0
0
R/W
IR3
28
12
−
R
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IR4
27
11
−
R
0
0
R/W
IR5
26
10
−
R
0
0
Description
Set priority of an independent interrupt request of IRQ0.
Set priority of an independent interrupt request of IRQ1.
Set priority of an independent interrupt request of IRQ2.
Set priority of an independent interrupt request of IRQ3.
Set priority of an independent interrupt request of IRQ4.
Set priority of an independent interrupt request of IRQ5.
Set priority of an independent interrupt request of IRQ6.
Set priority of an independent interrupt request of IRQ7.
R/W
IR6
25
−
R
0
9
0
R/W
IR7
24
−
R
0
8
0
23
−
−
R
R
0
7
0
22
R
R
−
0
6
−
0
21
−
R
−
R
0
5
0
20
R
R
−
0
4
−
0
19
R
R
−
−
0
3
0
18
−
R
−
R
0
2
0
17
−
R
−
R
0
1
0
16
−
R
−
R
0
0
0