R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1265

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
5
4
3 to 0
Bit Name
TXDIZ
RCIM
SYNCAC
SYNCDL
—
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
SIOF_TXD Pin Output when Transmission is Invalid*
0: High output (1 output) when invalid
1: High-impedance state when invalid
Note: Invalid means when disabled, and when a slot
Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
1: Sets the RCRDY bit in SISTR each time when the
SIOF_SYNC Pin Polarity
Valid when the SIOF_SYNC signal is output as a
synchronous pulse.
0: Active-high
1: Active-low
Data Pin Bit Delay for SIOF_SYNC Pin
Valid when the SIOF_SYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode. This bit should be set to 1.
0: No bit delay
1: 1-bit delay
Note: * When this bit is cleared to 0 (no bit delay is
Reserved
These bits are always read as 0. The write value should
always be 0.
SIRCR change.
SIRCR receives the control data.
that is not assigned as transmit data or control
data is being transmitted.
selected) in slave mode, the receive data is
sampled at the rising edge of SCK.
Rev. 2.00 May 22, 2009 Page 1195 of 1982
Section 29 Serial I/O with FIFO (SIOF)
REJ09B0256-0200