R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1163

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
27.3.14 Serial Error Register (SCRER)
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR.
SCRER can always be read from the CPU.
Initial value:
Bit
15, 14
13
12
11
10
9
8
7, 6
5
4
3
2
1
0
R/W:
BIt:
Bit Name
PER5
PER4
PER3
PER2
PER1
PER0
FER5
FER4
FER3
FER2
FER1
FER0
15
R
0
14
R
0
PER5
13
R
0
Initial
Value
All 0
0
0
0
0
0
0
All 0
0
0
0
0
0
0
PER4
12
R
0
PER3
11
R
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PER2
10
R
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Parity Errors
These bits indicate the number of data bytes in which a
parity error occurred in the receive data stored in
SCFRDR.
After the ER bit in SCFSR is set, the value indicated by
bits PER5 to PER0 is the number of data bytes in which
a parity error occurred.
If all 64 bytes of receive data in SCFRDR have parity
errors, the value indicated by bits PER5 to PER0 will be
0.
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Framing Errors
These bits indicate the number of data bytes in which a
framing error occurred in the receive data stored in
SCFRDR.
After the ER bit in SCFSR is set, the value indicated by
bits FER5 to FER0 is the number of data bytes in which
a framing error occurred.
If all 64 bytes of receive data in SCFRDR have framing
errors, the value indicated by bits FER5 to FER0 will be
0.
PER1
Section 27 Serial Communication Interface with FIFO (SCIF)
R
9
0
PER0
R
8
0
R
7
0
Rev. 2.00 May 22, 2009 Page 1093 of 1982
R
6
0
FER5
R
5
0
FER4
R
4
0
FER3
R
3
0
REJ09B0256-0200
FER2
R
2
0
FER1
R
1
0
FER0
R
0
0

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