R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 11

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview................................................................................................1
1.1
1.2
1.3
Section 2 Programming Model ............................................................................37
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Section 3 Instruction Set ......................................................................................57
3.1
3.2
3.3
Section 4 Pipelining .............................................................................................79
4.1
4.2
4.3
Section 5 Exception Handling ...........................................................................105
5.1
5.2
Features of the SH7763.......................................................................................................... 1
Block Diagram ..................................................................................................................... 13
Pin Arrangement .................................................................................................................. 14
Data Formats........................................................................................................................ 37
Register Descriptions ........................................................................................................... 38
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Memory-Mapped Registers.................................................................................................. 51
Data Formats in Registers .................................................................................................... 52
Data Formats in Memory ..................................................................................................... 52
Processing States.................................................................................................................. 53
Usage Note........................................................................................................................... 55
2.7.1
Execution Environment ....................................................................................................... 57
Addressing Modes ............................................................................................................... 59
Instruction Set ...................................................................................................................... 64
Pipelines............................................................................................................................... 79
Parallel-Executability........................................................................................................... 90
Issue Rates and Execution Cycles........................................................................................ 94
Summary of Exception Handling....................................................................................... 105
Register Descriptions ......................................................................................................... 105
5.2.1
5.2.2
5.2.3
Privileged Mode and Banks .................................................................................... 38
General Registers.................................................................................................... 42
Floating-Point Registers.......................................................................................... 43
Control Registers .................................................................................................... 45
System Registers..................................................................................................... 47
Notes on Self-Modified Codes................................................................................ 55
TRAPA Exception Register (TRA) ...................................................................... 106
Exception Event Register (EXPEVT)................................................................... 107
Interrupt Event Register (INTEVT)...................................................................... 108
Contents
Rev. 2.00 May 22, 2009 Page ix of lxviii