R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 61

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Table 1.1
Table 1.2
Section 2 Programming Model
Table 2.1
Table 2.2
Section 3 Instruction Set
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Section 4 Pipelining
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Section 5 Exception Handling
Table 5.1
Table 5.2
Table 5.3
Section 6 Memory Management Unit (MMU)
Table 6.1
Table 6.2
Features of the SH7763............................................................................................. 2
Pin Configuration.................................................................................................... 16
Initial Register Values............................................................................................. 40
Bit Allocation for FPU Exception Handling........................................................... 50
Execution Order of Delayed Branch Instructions ................................................... 57
Addressing Modes and Effective Addresses........................................................... 59
Notation Used in Instruction List............................................................................ 64
Fixed-Point Transfer Instructions ........................................................................... 66
Arithmetic Operation Instructions .......................................................................... 68
Logic Operation Instructions .................................................................................. 70
Shift Instructions..................................................................................................... 71
Branch Instructions ................................................................................................. 72
System Control Instructions.................................................................................... 72
Floating-Point Single-Precision Instructions .......................................................... 75
Floating-Point Double-Precision Instructions......................................................... 76
Floating-Point Control Instructions ........................................................................ 76
Floating-Point Graphics Acceleration Instructions ................................................. 77
Representations of Instruction Execution Patterns.................................................. 80
Instruction Groups .................................................................................................. 90
Combination of Preceding and Following Instructions........................................... 93
Issue Rates and Execution Cycles........................................................................... 95
Register Configuration.......................................................................................... 105
States of Register in Each Operating Mode .......................................................... 105
Exceptions............................................................................................................. 110
Register Configuration.......................................................................................... 146
Register States in Each Processing State .............................................................. 146
Tables
Rev. 2.00 May 22, 2009 Page lix of lxviii