R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1600

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 36 USB Function Controller (USBF)
36.3.19 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. The number of receive byte is displayed in
the EP1 receive data size register. The buffer on read side can be received again by writing
EP1RDFN in the trigger register to 1 after data is read. The receive data of this FIFO buffer can be
transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR0
register.
Rev. 2.00 May 22, 2009 Page 1530 of 1982
REJ09B0256-0200
Bit
31 to 8 
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
Bit Name
D[7:0]
R
R
30
14
R
R
29
13
R
R
Initial Value R/W Description
Undefined
Undefined
28
12
R
R
27
11
R
R
26
10
R
R
R
R
25
R
R
9
Data register for endpoint1 transfer
Reserved
These bits are always read as undefined value.
24
R
R
8
23
R
R
7
22
R
R
6
21
R
R
5
20
R
R
4
D[7:0]
19
R
R
3
18
R
R
2
17
R
R
1
16
R
R
0

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