R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 665

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer
destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer
request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive
data register. These conditions also apply to the SCIF1, SCIF2, HAC USBF, SSI0 to SSI3,
MMCIF, SIM, SIOF0 to SIOF2, STIF0, and STIF1.
Table 14.8 Selecting On-Chip Peripheral Module Request Modes with Bits RS[3:0]
CHCR
RS[3:0]
1000
MID
000000
000001
000010
000011
000100
001000
001010
010000
010001
010100
011100
DMARS
RID
11
11
11
11
11
01
10
01
10
01
10
01
10
01
10
11
11
CMT
DMA Transfer
Request
Source
channel 0
CMT channel
1
CMT channel
2
CMT channel
3
CMT channel
4
SCI F0
transmitter
SCIF0
receiver
SCI F1
transmitter
SCIF1
receiver
SCIF2
transmitter
SCIF2
receiver
HAC
transmitter
HAC
receiver
USB
transmitter
USB
receiver
SSI0
transmitter
SSI0
receiver
DMA Transfer
Request Signal
Compare-match transfer
request
Compare-match transfer
request
Compare-match transfer
request
Compare-match transfer
request
Compare-match transfer
request
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data
full interrupt)
TXI (transmit FIFO data
empty interrupt)
RXI (receive FIFO data full
interrupt)
Transmit data empty request Any
Receive data is not read
Transmit data empty request Any
Receive data full request
Transmit mode : DMRQ = 1
(Transmit data empty
request)
Receive mode : DMRQ = 1
(Receive data is not read)
Section 14 Direct Memory Access Controller (DMAC)
Rev. 2.00 May 22, 2009 Page 595 of 1982
Source
Any
Any
Any
Any
Any
Any
SCFRDR0
Any
SCFRDR1
Any
SCFRDR2
HACPCML,
HACPCMR
EPDR
Any
SSIRDR
Destination
Any
Any
Any
Any
Any
SCFTDR0
Any
SCFTDR1
Any
SCFTDR2
Any
HACPCML,
HACPCMR
Any
EPDR
Any
SSIRDR
Any
REJ09B0256-0200
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal